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DAC
2000
ACM
14 years 8 months ago
Convex delay models for transistor sizing
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapat...
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
14 years 1 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
Power gating has been widely used to reduce subthreshold leakage. However, its efficiency degrades very fast with technology scaling due to the gate leakage of circuits specific t...
Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun ...
DMDW
2003
269views Management» more  DMDW 2003»
13 years 9 months ago
CASME: A CASE Tool for Spatial Data Marts Design and Generation
Geographic Information Systems (GIS) showed their insufficiencies in front of complex requests for decision-makers. Resulting of the association of the databases and the decision-m...
Hajer Baazaoui Zghal, Sami Faïz, Henda Hajjam...
CCE
2007
13 years 9 months ago
A Web Services based Approach for System on a Chip Design Planning
: The concept of Virtual Organisation (VO) offers various solutions to management, collaboration and coordination issues important for distributed collaborating teams. Deployment o...
Maciej Witczynski, Edward Hrynkiewicz, Adam Pawlak