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DAC
2006
ACM
14 years 9 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
NOCS
2009
IEEE
14 years 2 months ago
Scalability of network-on-chip communication architecture for 3-D meshes
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuw...
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 2 months ago
A highly resilient routing algorithm for fault-tolerant NoCs
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will so...
David Fick, Andrew DeOrio, Gregory K. Chen, Valeri...
WACV
2002
IEEE
14 years 25 days ago
Monocular, Vision Based, Autonomous Refueling System
This paper describes design and implementation of a vision based platform for automated refueling tasks. The platform is an autonomous docking system in principle, with the specif...
Aly A. Farag, Emir Dizdarevic, Ahmed Eid, Albert L...
IPPS
2007
IEEE
14 years 2 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao