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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 4 months ago
A Probabilistic-Based Design Methodology for Nanoscale Computation
As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research p...
R. Iris Bahar, Joseph L. Mundy, Jie Chen
CODES
2003
IEEE
14 years 1 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
INFOCOM
1992
IEEE
13 years 11 months ago
Topological Design of Interconnected LAN-MAN Networks
This paper describes a methodology for designing interconnected LAN-MAN networks with the objective of minimizing the average network delay. We consider IEEE 802.3-5 LANs intercon...
Cem Ersoy, Shivendra S. Panwar
TCAD
2008
84views more  TCAD 2008»
13 years 7 months ago
Buffering Interconnect for Multicore Processor Designs
Recently, the microprocessor industry is headed in the direction of multicore designs in order to continue the chip performance growth. We investigate buffer insertion, which is a ...
Yifang Liu, Jiang Hu, Weiping Shi
ISQED
2008
IEEE
103views Hardware» more  ISQED 2008»
14 years 2 months ago
Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics
— Designers require variational information for robust designs. Characterization of such information can be costly for the novel nanoparticle interconnect process, which utilize ...
Rasit Onur Topaloglu