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ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
14 years 4 months ago
Design-Space Exploration of Power-Aware On/Off Interconnection Networks
— With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems....
Vassos Soteriou, Li-Shiuan Peh
DAC
2001
ACM
14 years 8 months ago
Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design
Communication-based design represents a formal approach to systemon-a-chip design that considers communication between components as important as the computations they perform. Ou...
Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Ke...
DATE
2006
IEEE
80views Hardware» more  DATE 2006»
14 years 1 months ago
Energy-efficient FPGA interconnect design
Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size...
Maurice Meijer, Rohini Krishnan, Martijn T. Benneb...
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 2 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
DAC
1999
ACM
14 years 10 hour ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung