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GLVLSI
2009
IEEE
112views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Simultaneous shield and repeater insertion
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum c...
Renatas Jakushokas, Eby G. Friedman
ISLPED
2003
ACM
83views Hardware» more  ISLPED 2003»
14 years 29 days ago
Leakage power modeling and optimization in interconnection networks
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
Xuning Chen, Li-Shiuan Peh
DAC
2004
ACM
14 years 8 months ago
Architecture-level synthesis for automatic interconnect pipelining
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
Jason Cong, Yiping Fan, Zhiru Zhang
DAC
2000
ACM
14 years 8 months ago
On switch factor based analysis of coupled RC interconnects
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
DEBU
2006
166views more  DEBU 2006»
13 years 7 months ago
Oracle's Self-Tuning Architecture and Solutions
Performance tuning in modern database systems requires a lot of expertise, is very time consuming and often misdirected. Tuning attempts often lack a methodology that has a holist...
Benoît Dageville, Karl Dias