Sciweavers

434 search results - page 25 / 87
» Design Methodologies and Architecture Solutions for High-Per...
Sort
View
DAC
1999
ACM
14 years 1 days ago
Buffer Insertion with Accurate Gate and Interconnect Delay Computation
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
SAC
2009
ACM
14 years 11 days ago
The device service bus: a solution for embedded device integration through web services
This paper presents a middleware infrastructure for integration of heterogeneous embedded devices in ubiquitous computing environments. The proposed infrastructure employs the Dev...
Gustavo Medeiros Araújo, Frank Siqueira
DATE
2010
IEEE
192views Hardware» more  DATE 2010»
14 years 24 days ago
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
Johnnie Chan, Gilbert Hendry, Aleksandr Biberman, ...
DAC
2009
ACM
14 years 2 months ago
Variational capacitance extraction of on-chip interconnects based on continuous surface model
In this paper we present a continuous surface model to describe the interconnect geometric variation, which improves the currently used model for better accuracy while not increas...
Wenjian Yu, Chao Hu, Wangyang Zhang
VLSID
2002
IEEE
109views VLSI» more  VLSID 2002»
14 years 8 months ago
Probabilistic Analysis of Rectilinear Steiner Trees
Steiner tree is a fundamental problem in the automatic interconnect optimization for VLSI design. We present a probabilistic analysis method for constructing rectilinear Steiner t...
Chunhong Chen