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» Design Patterns for Reconfigurable Computing
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VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
14 years 9 months ago
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaud...
FPL
2004
Springer
164views Hardware» more  FPL 2004»
14 years 14 days ago
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors
Abstract. In Reconfigurable Systems-On-Chip (RSoCs), operating systems can primarily (1) manage the sharing of limited reconfigurable resources, and (2) support communication betwe...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
ERSA
2010
186views Hardware» more  ERSA 2010»
13 years 6 months ago
DAPR: Design Automation for Partially Reconfigurable FPGAs
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
Shaon Yousuf, Ann Gordon-Ross
FPL
2010
Springer
105views Hardware» more  FPL 2010»
13 years 6 months ago
Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options
Exotic options are financial derivatives which have complex features including path-dependency. These complex features make them difficult to price, as only computationally intensi...
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, ...
FPL
2000
Springer
96views Hardware» more  FPL 2000»
14 years 10 days ago
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures
Coarse-grain reconfigurable architectures have been a matter of intense research in the last few years. They promise to be more adequate for computational tasks due to their better...
Reiner W. Hartenstein, Michael Herz, Thomas Hoffma...