605 search results - page 51 / 121 » Design Principles for Combiners with Memory |
3DPVT
2004
IEEE
14 years 14 days ago
2004
IEEE
In this paper, we propose a viewer for huge point-sampled models by combining out-of-core technologies with view-dependent level-of-detail (LOD) control. This viewer is designed o...
IPPS
1999
IEEE
14 years 1 months ago
1999
IEEE
In order for parallel logic programming systems to become popular, they should serve the broadest range of applications. To achieve this goal, designers of parallel logic programm...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the lo...
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
TVLSI
2010
13 years 3 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...