50 search results - page 2 / 10 » Design Rewiring Using ATPG |
ETS
2010
IEEE
13 years 8 months ago
2010
IEEE
It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially ...
ATS
2003
IEEE
14 years 10 days ago
2003
IEEE
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
ETS
2009
IEEE
2009
IEEE
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
13 years 4 months ago
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
ITC
2002
IEEE
13 years 12 months ago
2002
IEEE
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
DT
2000
13 years 6 months ago
2000
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...