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ICCAD
1999
IEEE
125views Hardware» more  ICCAD 1999»
15 years 9 months ago
Direct synthesis of timed asynchronous circuits
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
Sung Tae Jung, Chris J. Myers
CVGIP
2006
115views more  CVGIP 2006»
15 years 5 months ago
Methods for exploring expressive stance
The postures a character adopts over time are a key expressive aspect of her movement. While IK tools help a character achieve positioning constraints, there are few tools that he...
Michael Neff, Eugene Fiume
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
15 years 8 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
DAC
2008
ACM
16 years 6 months ago
Specify-explore-refine (SER): from specification to implementation
Driven by increasing complexity and reliability demands, the Japanese Aerospace Exploration Agency (JAXA) in 2004 commissioned development of ELEGANT, a complete SpecC-based envir...
Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Dani...
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 7 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie