153 search results - page 21 / 31 » Design Space Exploration in System Level Synthesis under Mem... |
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
CVGIP
2006
13 years 7 months ago
2006
The postures a character adopts over time are a key expressive aspect of her movement. While IK tools help a character achieve positioning constraints, there are few tools that he...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Driven by increasing complexity and reliability demands, the Japanese Aerospace Exploration Agency (JAXA) in 2004 commissioned development of ELEGANT, a complete SpecC-based envir...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...