Sciweavers

5 search results - page 1 / 1
» Design Trade-offs in Customized On-chip Crossbar Schedulers
Sort
View
ASAP
2007
IEEE
150views Hardware» more  ASAP 2007»
13 years 11 months ago
Customizing Reconfigurable On-Chip Crossbar Scheduler
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...
ARC
2007
Springer
116views Hardware» more  ARC 2007»
14 years 1 months ago
Systematic Customization of On-Chip Crossbar Interconnects
Abstract. In this paper, we present a systematic design and implementation of reconfigurable interconnects on demand. The proposed on-chip interconnection network provides identic...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...
IPPS
2002
IEEE
14 years 14 days ago
Hierarchical Interconnects for On-Chip Clustering
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
Aneesh Aggarwal, Manoj Franklin
VLSISP
2010
80views more  VLSISP 2010»
13 years 5 months ago
Design Trade-offs in Customized On-chip Crossbar Schedulers
Jae Young Hur, Stephan Wong, Todor Stefanov
DAC
1998
ACM
13 years 11 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha