Sciweavers

870 search results - page 104 / 174
» Design Tradeoffs for SSD Performance
Sort
View
DAC
2003
ACM
15 years 9 months ago
Realizable RLCK circuit crunching
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Isma...
DAC
2005
ACM
15 years 6 months ago
Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation
On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem ext...
Peng Li
TVLSI
2010
14 years 10 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li
CASES
2006
ACM
15 years 10 months ago
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
Mark Hempstead, Gu-Yeon Wei, David Brooks
140
Voted
INFOCOM
2005
IEEE
15 years 9 months ago
On the maximal throughput of networks with finite buffers and its application to buffered crossbars
— The advent of packet networks has motivated many researchers to study the performance of networks of queues in the last decade or two. However, most of the previous work assume...
Paolo Giaccone, Emilio Leonardi, Devavrat Shah