665 search results - page 19 / 133 » Design and Analysis of a Dynamically Reconfigurable Network ... |
ASPDAC
2007
ACM
14 years 1 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
TIM
2010
13 years 3 months ago
2010
In this paper, the authors propose and analyze a network-based control architecture for power-electronicsbuilding-block-based converters. The objective of the proposed approach is ...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
DAC
2002
ACM
14 years 10 months ago
2002
ACM
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...