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WSC
1998
13 years 10 months ago
Warehouse Design through Dynamic Simulation
Intel's new processors in mid-1997 were a dramatic increased in speed and size over their ancestors. The increased size caused box volume to increase beyond the capacity of t...
Mark Kosfeld
CODES
2002
IEEE
14 years 2 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
APCCAS
2006
IEEE
373views Hardware» more  APCCAS 2006»
14 years 23 days ago
A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...
Vipul Katyal, Randall L. Geiger, Degang Chen
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
14 years 3 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
SECON
2010
IEEE
13 years 7 months ago
QoI-Aware Wireless Sensor Network Management for Dynamic Multi-Task Operations
Abstract--This paper considers the novel area of quality-ofinformation (QoI)-aware network management of multitasking wireless sensor networks (WSNs). Specifically, it provides an ...
Chi Harold Liu, Chatschik Bisdikian, Joel W. Branc...