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DSD
2010
IEEE
153views Hardware» more  DSD 2010»
15 years 4 months ago
Simulation of High-Performance Memory Allocators
—Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern highperformance applications. To optimize metrics like performance, memory us...
José Luis Risco-Martín, José ...
CASES
2003
ACM
15 years 9 months ago
Reducing code size with echo instructions
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood...
EUROMICRO
2007
IEEE
15 years 10 months ago
A Performance Evaluation of RSerPool Server Selection Policies in Varying Heterogeneous Capacity Scenarios
Reliable Server Pooling (RSerPool) is a protocol framework for server redundancy and session failover, currently still under standardization by the IETF RSerPool WG. Server redund...
Thomas Dreibholz, Xing Zhou, Erwin P. Rathgeb
MICRO
2009
IEEE
137views Hardware» more  MICRO 2009»
15 years 10 months ago
ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem
Dynamic Random Access Memory (DRAM) is used as the bulk of the main memory in most computing systems and its energy and power consumption has become a first-class design considera...
Ciji Isen, Lizy Kurian John
121
Voted
HPCA
2001
IEEE
16 years 4 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger