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ICS
1993
Tsinghua U.
13 years 11 months ago
Anatomy of a Message in the Alewife Multiprocessor
Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is often implemented with a layer of interpretive hardware on top of a message-pas...
John Kubiatowicz, Anant Agarwal
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 2 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...
IPPS
2000
IEEE
14 years 2 days ago
Switch Scheduling in the Multimedia Router (MMR)
The primary goal of the Multimedia Router (MMR) project is the design and implementation of a router optimized for multimedia applications. The router is targeted for use in clust...
Damon S. Love, Sudhakar Yalamanchili, José ...
CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
CLUSTER
2005
IEEE
14 years 1 months ago
Supporting iWARP Compatibility and Features for Regular Network Adapters
With several recent initiatives in the protocol offloading technology present on network adapters, the user market is now distributed amongst various technology levels including r...
Pavan Balaji, Hyun-Wook Jin, Karthikeyan Vaidyanat...