47 search results - page 7 / 10 » Design and Implementation of Scalable Low-Power Montgomery M... |
ISLPED
1999
ACM
13 years 11 months ago
1999
ACM
A recent trend in low power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs c...
CDES
2006
13 years 9 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
IAJIT
2006
13 years 7 months ago
2006
In this paper, a fast hardware architecture for elliptic curve cryptography computation in Galois Field GF(p) is proposed. The architecture is implemented for 160-bits, as its dat...
GLVLSI
2003
IEEE
14 years 24 days ago
2003
IEEE
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
We present the architecture of digit-serial normal basis multiplier over GF(2m ). The multiplier was derived from the multiplier of Agnew et al. Proposed multiplier is scalable by...