Sciweavers

222 search results - page 11 / 45
» Design and Implementation of Semi-preemptible IO
Sort
View
ICDCS
2010
IEEE
13 years 11 months ago
A New Buffer Cache Design Exploiting Both Temporal and Content Localities
: This paper presents a Least Popularly Used buffer cache algorithm to exploit both temporal locality and content locality of I/O requests. Popular data blocks are selected as refe...
Jin Ren, Qing Yang
FPGA
2005
ACM
174views FPGA» more  FPGA 2005»
14 years 1 months ago
64-bit floating-point FPGA matrix multiplication
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G...
DAC
2002
ACM
14 years 8 months ago
Deriving a simulation input generator and a coverage metric from a formal specification
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
Kanna Shimizu, David L. Dill
SIGMETRICS
1998
ACM
112views Hardware» more  SIGMETRICS 1998»
13 years 12 months ago
Implementing Cooperative Prefetching and Caching in a Globally-Managed Memory System
This paper presents cooperative prefetching and caching — the use of network-wide global resources (memories, CPUs, and disks) to support prefetching and caching in the presence...
Geoffrey M. Voelker, Eric J. Anderson, Tracy Kimbr...
ISLPED
1996
ACM
68views Hardware» more  ISLPED 1996»
13 years 11 months ago
Energy-recovery CMOS for highly pipelined DSP designs
We compare the frequency-versus-power dissipation performance of two energy-recovery CMOS implementations to that of a conventional, supply-voltage-scaled design. The application ...
William C. Athas, W.-C. Liu, Lars J. Svensson