71 search results - page 4 / 15 » Design and Implementation of a High Speed Microprocessor Sim... |
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
SAMOS
2004
Springer
14 years 1 months ago
2004
Springer
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
ISLPED
2003
ACM
14 years 29 days ago
2003
ACM
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
HPCA
2005
IEEE
14 years 1 months ago
2005
IEEE
As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increas...
ARVLSI
1997
IEEE
13 years 12 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...