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ISCAS
1993
IEEE
125views Hardware» more  ISCAS 1993»
15 years 8 months ago
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback
- A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read poin...
Gennady Feygin, Paul Chow, P. Glenn Gulak, John Ch...
ICCAD
1994
IEEE
105views Hardware» more  ICCAD 1994»
15 years 8 months ago
Register assignment through resource classification for ASIP microcode generation
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
Clifford Liem, Trevor C. May, Pierre G. Paulin
FPL
2010
Springer
129views Hardware» more  FPL 2010»
15 years 2 months ago
FPGA Implementations of the Round Two SHA-3 Candidates
Abstract--The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper present...
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilt...
IWAN
2000
Springer
15 years 7 months ago
A Flexible IP Active Networks Architecture
This paper presents the main concepts of the IST Project FAIN "Future Active IP Networks" [10], a three-year collaborative research project, whose main task is to develo...
Alex Galis, Bernhard Plattner, Jonathan M. Smith, ...
PUC
2008
113views more  PUC 2008»
15 years 3 months ago
A resource and context model for mobile middleware
Abstract Mobile computing systems should be selfmanaged to simplify operation and maintenance plus meet user's expectation with respect to Quality of Service (QoS). When archi...
Sten Lundesgaard Amundsen, Frank Eliassen