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DSD
2010
IEEE
221views Hardware» more  DSD 2010»
13 years 5 months ago
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...
ERSA
2007
174views Hardware» more  ERSA 2007»
13 years 9 months ago
High-Level Specification of Runtime Reconfigurable Designs
”C to Gates” compilers for FPGAs have been a topic of investigation for nearly two decades. Some of these endeavors have reached a point of viability. Impulse C, for example, ...
Stephen D. Craven, Peter M. Athanas
DATE
2008
IEEE
153views Hardware» more  DATE 2008»
14 years 2 months ago
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications
Novel reconfigurable computing platforms enable efficient realizations of complex signal processing applications by allowing exploitation of parallelization resulting in high thro...
Sankalita Saha, Jason Schlessman, Sebastian Puthen...
DAC
2008
ACM
14 years 8 months ago
Partial order reduction for scalable testing of systemC TLM designs
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we f...
Sudipta Kundu, Malay K. Ganai, Rajesh Gupta
CODES
2010
IEEE
13 years 4 months ago
Hardware/software optimization of error detection implementation for real-time embedded systems
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
Adrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izo...