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» Design and Implementation of the Memory Scheduler for the PC...
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CF
2007
ACM
15 years 10 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
RTSS
2000
IEEE
15 years 10 months ago
Scalable Real-Time System Design using Preemption Thresholds
The maturity of schedulabilty analysis techniquesfor fired-prioritypreemptive scheduling has enabled the consideration of timing issues at design time using a specification of the...
Manas Saksena, Yun Wang
CODES
2007
IEEE
16 years 16 days ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
ICPP
1993
IEEE
15 years 10 months ago
Activity Counter: New Optimization for the Dynamic Scheduling of SIMD Control Flow
SIMD or vector computers and collection-oriented languages, like C , are designed to perform the same computation on each data item or on just a subset of the data. Subsets of pro...
Ronan Keryell, Nicolas Paris
DAC
2006
ACM
16 years 7 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...