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» Design and application of multimodal power gating structures
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ISLPED
2004
ACM
149views Hardware» more  ISLPED 2004»
14 years 2 months ago
Creating a power-aware structured ASIC
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectur...
R. Reed Taylor, Herman Schmit
ISLPED
2006
ACM
119views Hardware» more  ISLPED 2006»
14 years 2 months ago
Process variation aware cache leakage management
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Ke Meng, Russ Joseph
SLIP
2009
ACM
14 years 3 months ago
Predicting the worst-case voltage violation in a 3D power network
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shaya...
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
14 years 2 months ago
Design and test of fixed-point multimedia co-processor for mobile applications
: In this research, a fixed-point multimedia co-processor is designed and tested into an ARM-10 based mobile graphics processor for portable 2-D and 3-D multimedia applications. Th...
Ju-Ho Sohn, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo
ISCAS
2008
IEEE
120views Hardware» more  ISCAS 2008»
14 years 3 months ago
Improving the power-delay product in SCL circuits using source follower output stage
— This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay...
Armin Tajalli, Frank K. Gürkaynak, Yusuf Lebl...