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» Design and application of multimodal power gating structures
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ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
14 years 2 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
14 years 2 months ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ASPLOS
2004
ACM
14 years 2 months ago
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkar...
DSN
2007
IEEE
14 years 3 months ago
Using Register Lifetime Predictions to Protect Register Files against Soft Errors
— Device scaling and large integration increase the vulnerability of microprocessors to transient errors. One of the structures where errors can be most harmful is the register ï...
Pablo Montesinos, Wei Liu, Josep Torrellas
IJCNN
2000
IEEE
14 years 1 months ago
Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata
This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Te...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...