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» Design and application of multimodal power gating structures
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AIA
2007
13 years 10 months ago
Minimizing leakage: What if every gate could have its individual threshold voltage?
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...
Ralf Salomon, Frank Sill, Dirk Timmermann
ICMI
2005
Springer
107views Biometrics» more  ICMI 2005»
14 years 2 months ago
Exploring multimodality in the laboratory and the field
There are new challenges to us, as researchers, on how to design and evaluate new mobile applications because they give users access to powerful computing devices through small in...
Lynne Baillie, Raimund Schatz
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
14 years 2 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...
ICCAD
1997
IEEE
75views Hardware» more  ICCAD 1997»
14 years 27 days ago
An exact gate decomposition algorithm for low-power technology mapping
With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In...
Hai Zhou, D. F. Wong
ICCAD
2002
IEEE
80views Hardware» more  ICCAD 2002»
14 years 5 months ago
Minimizing power across multiple technology and design levels
Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage curr...
Takayasu Sakurai