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MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
14 years 1 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
ASPDAC
2004
ACM
132views Hardware» more  ASPDAC 2004»
14 years 5 days ago
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications
– A low-power graphics LSI is designed and implemented for mobile multimedia applications. The LSI contains a 32bit RISC processor with enhanced MAC, a 3D rendering engine, progr...
Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun S...
WMPI
2004
ACM
14 years 4 days ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 24 days ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
CODES
2007
IEEE
14 years 1 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha