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NOCS
2009
IEEE
14 years 1 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
14 years 20 days ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
MTV
2003
IEEE
109views Hardware» more  MTV 2003»
13 years 12 months ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt
WMCSA
2003
IEEE
13 years 12 months ago
River: An Infrastructure for Context Dependent, Reactive Communication Primitives
Applications and services in ubiquitous computing systems often interact in a context-dependent, reactive manner. How information flows, and what services communicate when, is det...
Jong Hee Kang, Matthai Philipose, Gaetano Borriell...
FPL
2007
Springer
94views Hardware» more  FPL 2007»
14 years 27 days ago
An OCM based shared Memory controller for Virtex 4
In this paper, we present a shared instruction and data memory controller for the On-Chip Memory (OCM) bus of the PowerPC embedded in the Virtex-4 chip. The traditional design of ...
Bas Breijer, Filipa Duarte, Stephan Wong