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TVLSI
2010
13 years 2 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
13 years 11 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
DATE
2010
IEEE
263views Hardware» more  DATE 2010»
14 years 15 days ago
SCOC3: a space computer on a chip
—This paper presents the definition of an integrated processor core ASIC named SCOC3 which is designed for space computers. It also presents the validation method that has led to...
Franck Koebel, Jean-François Coldefy
DAC
2010
ACM
13 years 11 months ago
Circuit modeling for practical many-core architecture design exploration
Current tools for computer architecture design lack standard support for multi- and many-core development. We propose using circuit models to describe the multiple processor archi...
Dean Truong, Bevan M. Baas
TVLSI
2002
118views more  TVLSI 2002»
13 years 7 months ago
A microcoded elliptic curve processor using FPGA technology
The implementation of a microcoded elliptic curve processor using field-programmable gate array technology is described. This processor implements optimal normal basis field operat...
Philip Heng Wai Leong, Ivan K. H. Leung