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» Design and evaluation of an auto-memoization processor
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149
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HPDC
2010
IEEE
15 years 4 months ago
A GPU accelerated storage system
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
Abdullah Gharaibeh, Samer Al-Kiswany, Sathish Gopa...
ICCD
2008
IEEE
109views Hardware» more  ICCD 2008»
16 years 1 months ago
Suitable cache organizations for a novel biomedical implant processor
— This paper evaluates various instruction- and data-cache organizations in terms of performance, power, energy and area on a suitably selected biomedical benchmark suite. The be...
Christos Strydis
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
15 years 10 months ago
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations...
Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, G...
RTSS
2006
IEEE
15 years 10 months ago
Processor Scheduler for Multi-Service Routers
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A sc...
Ravi Kokku, Upendra Shevade, Nishit Shah, Ajay Mah...
133
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GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
15 years 9 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi