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» Design and implementation of JPEG encoder IP core
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DSD
2010
IEEE
144views Hardware» more  DSD 2010»
13 years 7 months ago
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
IJNSEC
2010
247views more  IJNSEC 2010»
13 years 2 months ago
Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves
The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and imp...
Sameh M. Shohdy, Ashraf El-Sisi, Nabil A. Ismail
SBCCI
2003
ACM
213views VLSI» more  SBCCI 2003»
14 years 19 days ago
Algorithms and Tools for Network on Chip Based System Design
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
Tang Lei, Shashi Kumar
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
14 years 1 months ago
Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor
A generic and retargetable tool flow is presented that enables the export of timing data from software running on a cycle-accurate Virtual Prototype (VP) to a concurrent function...
Trevor Meyerowitz, Alberto L. Sangiovanni-Vincente...
HICSS
2003
IEEE
125views Biometrics» more  HICSS 2003»
14 years 20 days ago
Applying a Layered Policy Model to IP Based Voice Services
Traditionally, specific telecommunications services were essentially confined to certain types of networks; e.g., television over broadcast networks or cable and voice service ove...
Douglas C. Sicker