189 search results - page 24 / 38 » Design and implementation of WIRE Diameter |
VLSID
2005
IEEE
14 years 10 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
PATMOS
2004
Springer
14 years 3 months ago
2004
Springer
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
PDP
2010
IEEE
14 years 2 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
ICCD
2007
IEEE
14 years 6 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
AGENTS
1997
Springer
14 years 2 months ago
1997
Springer
During the last few years, and in an attempt to provide an ecient alternative to classical methods to designing robot control structures, the behavior-based approach has emerged....