189 search results - page 32 / 38 » Design and implementation of WIRE Diameter |
DAC
1999
ACM
14 years 10 months ago
1999
ACM
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...
COMSWARE
2006
IEEE
14 years 1 months ago
2006
IEEE
Applications using traditional protocol stacks (e.g TCP/IP) from wired networks do not function efficiently in mobile wireless scenarios. This is primarily due to the layered archi...
ASAP
2002
IEEE
14 years 2 months ago
2002
IEEE
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be sup...
GLVLSI
2010
IEEE
14 years 3 months ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
AAAI
1998
13 years 11 months ago
1998
This paper discusses the design and implementation of ESSPL, an expert system which generates security plans for alarm systems (Figure 1). Security planning is the task of determi...