788 search results - page 19 / 158 » Design and use of a system-level specification and verificat... |
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
POPL
2005
ACM
14 years 7 months ago
2005
ACM
While a typical software component has a clearly specified (static) interface in terms of the methods and the input/output types they support, information about the correct sequen...
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
ISQED
2002
IEEE
14 years 10 days ago
2002
IEEE
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...
VSTTE
2005
Springer
14 years 27 days ago
2005
Springer
The grand challenge that is the focus of this conference targets the development of a practical methodology for software verification: a methodology that can help us to reduce the ...