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» Design considerations for MRAM
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VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
16 years 5 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
ICSE
2007
IEEE-ACM
16 years 4 months ago
Is Code Still Moving Around? Looking Back at a Decade of Code Mobility
In the mid-nineties, mobile code was on the rise and, in particular, there was a growing interest in autonomously moving code components, called mobile agents. In 1997, we publish...
Antonio Carzaniga, Gian Pietro Picco, Giovanni Vig...
ICCAD
2005
IEEE
121views Hardware» more  ICCAD 2005»
16 years 1 months ago
Transition-by-transition FSM traversal for reachability analysis in bounded model checking
Abstract— In bounded model checking (BMC)-based verification flows lack of reachability constraints often leads to false negatives. At present, it is daily practice of a veri...
Minh D. Nguyen, Dominik Stoffel, Markus Wedler, Wo...
GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
15 years 11 months ago
Timing-driven N-way decomposition
Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techni...
David Bañeres, Jordi Cortadella, Michael Ki...
ISCAS
2008
IEEE
160views Hardware» more  ISCAS 2008»
15 years 11 months ago
ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework
— This paper presents ATLAS - a framework for automated analog circuit synthesis that comprises of both topology generation and subsequent circuit sizing. A hierarchically arrang...
Angan Das, Ranga Vemuri