59 search results - page 7 / 12 » Design for Verification in System-level Models and RTL |
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Most of the challenges related to the development of multi-processor platforms for complex wireless and multimedia applications fall into the Electronic System Level (ESL) domain....
ISSS
2002
IEEE
14 years 13 days ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...