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ASPDAC
1998
ACM
97views Hardware» more  ASPDAC 1998»
15 years 8 months ago
A Novel Design Assistant for Analog Circuits
 This paper presents a new design assistant for analog integrated circuits. The interactive tool is implemented in the Design Framework II of Cadence and supports the designer d...
Markus Wolf, Ulrich Kleine, Frédéric...
TEC
2008
97views more  TEC 2008»
15 years 4 months ago
Ergonomic Chair Design by Fusing Qualitative and Quantitative Criteria Using Interactive Genetic Algorithms
This paper emphasizes the necessity of formally bringing qualitative and quantitative criteria of ergonomic design together, and provides a novel complementary design framework wit...
Alexandra Melike Brintrup, Jeremy Ramsden, Hideyuk...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 10 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
CSDA
2008
56views more  CSDA 2008»
15 years 4 months ago
Robust designs for series estimation
We discuss optimal design problems for a popular method of series estimation in regression problems. Commonly used design criteria are based on the generalized variance of the est...
Holger Dette, Douglas P. Wiens
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 9 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri