Sciweavers

88 search results - page 7 / 18
» Design for manufacturability in submicron domain
Sort
View
VLSID
2002
IEEE
159views VLSI» more  VLSID 2002»
14 years 8 months ago
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
Karanth Shankaranarayana, Soujanna Sarkar, R. Venk...
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
14 years 1 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
HIS
2009
13 years 5 months ago
Design Methodology of a Fault Aware Controller Using an Incipient Fault Diagonizer
The problem of failure diagnosis has received a considerable attention in the domain of reliability engineering, process control and computer science. The increasing stringent req...
Joydeb Roychoudhury, Tribeni Prasad Banerjee, Anup...
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
14 years 1 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
DAC
2004
ACM
14 years 29 days ago
Optical proximity correction (OPC): friendly maze routing
As the technology migrates into the deep submicron manufacturing (DSM) era, the critical dimension of the circuits is getting smaller than the lithographic wavelength. The unavoid...
Li-Da Huang, Martin D. F. Wong