3 search results - page 1 / 1 » Design for testability using register-transfer level partial... |
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is ...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...