231 search results - page 38 / 47 » Design issues for dynamic voltage scaling |
CDES
2008
13 years 8 months ago
2008
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...
NOCS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
SIGOPS
2008
13 years 5 months ago
2008
Power management strategies for embedded systems typically rely on static, application driven deactivation of components (e.g. sleep, suspend), or on dynamic voltage and frequency...
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...