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» Design methodology for digital signal processing
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FPL
1999
Springer
103views Hardware» more  FPL 1999»
14 years 1 months ago
IP Validation for FPGAs Using Hardware Object Technology
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
Steve Casselman, John Schewel, Christophe Beaumont
ISCAS
1994
IEEE
66views Hardware» more  ISCAS 1994»
14 years 1 months ago
High Speed FIR-Filter Architectures with Scalable Sample Rates
FIR ( nite impulse response) lters are widely used in digital signal processing. In this paper new architectures for high speed FIR lters with programmable coe cients are presente...
Martin Vaupel, Heinrich Meyr
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
14 years 1 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
FPL
2008
Springer
154views Hardware» more  FPL 2008»
13 years 10 months ago
Numerical function generators using bilinear interpolation
Two-variable numerical functions are widely used in various applications, such as computer graphics and digital signal processing. Fast and compact hardware implementations are re...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
KES
2006
Springer
13 years 9 months ago
Implementation of a FIR Filter on a Partial Reconfigurable Platform
This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a ...
Hanho Lee, Chang-Seok Choi