In this paper we present a method formodeling asynchronous digital circuits by timed automata. The constructed timed automata serve as \mechanical" and veri able objects for a...
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks i...
Alexander Taubin, Jordi Cortadella, Luciano Lavagn...
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at...
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
Wendy Belluomini, Chris J. Myers, H. Peter Hofstee