253 search results - page 13 / 51 » Design of a logic element for implementing an asynchronous F... |
122
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IPPS
2006
IEEE
15 years 11 months ago
2006
IEEE
Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices...
113
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EUROPAR
2007
Springer
15 years 11 months ago
2007
Springer
We present in detail a GCA (Global Cellular Automaton) algorithm with 3n cells for Hirschberg’s algorithm which determines the connected components of a n-node undirected graph w...
153
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FPGA
1998
ACM
15 years 9 months ago
1998
ACM
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA...
150
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FPGA
2005
ACM
15 years 10 months ago
2005
ACM
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
129
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MEMOCODE
2010
IEEE
15 years 2 months ago
2010
IEEE
This paper presents a working solution for the MEMOCODE 2010 design contest. The design presented in this paper is implemented in the Xilinx V5LX330 FPGA as a custom circuit. The s...