253 search results - page 27 / 51 » Design of a logic element for implementing an asynchronous F... |
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Today’s network intrusion prevention systems (IPSs) must perform increasingly sophisticated analysis—parsing protocols and interpreting application dialogs rather than simply ...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
FPGA
2012
ACM
12 years 3 months ago
2012
ACM
In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemente...
ISSS
2002
IEEE
14 years 18 days ago
2002
IEEE
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...