253 search results - page 5 / 51 » Design of a logic element for implementing an asynchronous F... |
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Tw...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
AC
2002
Springer
13 years 7 months ago
2002
Springer
Abstract. Delay-Insensitive Sequential Processes is a structured, parallel programming language. It facilitates the clear, succinct and precise specification of the way an asynchro...
ICCD
1992
IEEE
13 years 11 months ago
1992
IEEE
We describe a new synthesis procedure for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental m...
FPL
1997
Springer
13 years 11 months ago
1997
Springer
Protocol Boosters are functional elements, inserted anddeleted fromnetwork protocol stacks on an as-neededbasis. The Protocol Booster design methodology attempts to improve end-to-...