195 search results - page 1 / 39 » Design of clocked circuits using UML |
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
– Clocking is an essential component of any embedded system design. However, traditional design techniques are either short of clocking support or too complex for users. The Unif...
ASPDAC
2000
ACM
13 years 11 months ago
2000
ACM
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...
ISLPED
2000
ACM
13 years 10 months ago
2000
ACM
This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
ISQED
2003
IEEE
14 years 8 days ago
2003
IEEE
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme fo...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...