Low power sequential circuit design by using priority encoding and clock gating

This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. The basic idea is to assign multiple codes to states so as to enable more effective clock gating in the sequential circuit. Practical design examples are studied and simulated by PSPICE. Experimental results demonstrate that the priority encoding technique can result in sizable power saving.

• Type: Conference
• Year: 2000
• Where: ISLPED
• Authors: Xunwei Wu, Massoud Pedram
• Keywords: Clock Gating, Effective Clock Gating, Hardware, ISLPED 2000, Sequential Circuit