55 search results - page 9 / 11 » Design of mixed gates for leakage reduction |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—On-chip decoupling capacitors (decaps) are generally used to reduce power supply noise. Passive decap designs are reaching their limits in 90nm CMOS technology due to higher ope...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
TCAD
2008
13 years 7 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...