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» Design optimizations for microprocessors at low temperature
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ICCD
2005
IEEE
109views Hardware» more  ICCD 2005»
14 years 4 months ago
Optimizing the Thermal Behavior of Subarrayed Data Caches
Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density...
Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
ISQED
2008
IEEE
118views Hardware» more  ISQED 2008»
14 years 1 months ago
A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors
In multi-core processors there are several ways to pair a thread to a particular core. These load-balancing techniques result in a quite different power, performance and thermal b...
Enric Musoll
FTEDA
2008
75views more  FTEDA 2008»
13 years 7 months ago
Thermally Aware Design
With greater integration, the power dissipation in integrated circuits has begun to outpace the ability of today's heat sinks to limit the on-chip temperature. As a result, t...
Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
14 years 2 months ago
Exploiting narrow-width values for thermal-aware register file designs
—Localized heating-up creates thermal hotspots across the chip, with the integer register file ranked as the hottest unit in high-performance microprocessors. In this paper, we ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras, Sung Woo ...
ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
14 years 1 months ago
Thermal-induced leakage power optimization by redundant resource allocation
Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage wou...
Min Ni, Seda Ogrenci Memik