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» Design space exploration of caches using compressed traces
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FPL
2007
Springer
97views Hardware» more  FPL 2007»
13 years 11 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
IJHPCA
2010
117views more  IJHPCA 2010»
13 years 5 months ago
Fine-Grained Multithreading Support for Hybrid Threaded MPI Programming
As high-end computing systems continue to grow in scale, recent advances in multiand many-core architectures have pushed such growth toward more denser architectures, that is, mor...
Pavan Balaji, Darius Buntinas, David Goodell, Will...
DATE
2009
IEEE
81views Hardware» more  DATE 2009»
14 years 2 months ago
ReSim, a trace-driven, reconfigurable ILP processor simulator
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...
Sotiria Fytraki, Dionisios N. Pnevmatikatos
CIDR
2009
157views Algorithms» more  CIDR 2009»
13 years 8 months ago
Capturing Data Uncertainty in High-Volume Stream Processing
We present the design and development of a data stream system that captures data uncertainty from data collection to query processing to final result generation. Our system focuse...
Yanlei Diao, Boduo Li, Anna Liu, Liping Peng, Char...
ASPLOS
2006
ACM
13 years 9 months ago
Tradeoffs in fine-grained heap memory protection
Different uses of memory protection schemes have different needs in terms of granularity. For example, heap security can benefit from chunk separation (by using protected "pa...
Jianli Shen, Guru Venkataramani, Milos Prvulovic