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CODES
2004
IEEE
15 years 9 months ago
Automatic synthesis of system on chip multiprocessor architectures for process networks
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishna...
ICDCSW
2008
IEEE
16 years 16 days ago
RETROFIT: Reliable Exchanges through Resilient Overlays for Internet Teleoperation
Emergence of successful teleoperation applications requires the convergence of diverse domains like robotics, machine learning, sensing, actuation, control and communication. We e...
Invited Talk Lakshamanan, Raj Rajkumar
163
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SAMOS
2005
Springer
15 years 11 months ago
Micro-architecture Performance Estimation by Formula
An analytical performance model for out of order issue superscalar micro-processors is presented. This model quantifies the performance impacts of micro-architecture design option...
Lucanus J. Simonson, Lei He
ACMACE
2009
ACM
16 years 18 days ago
iSee: interactive scenario explorer for online tournament games
Fantasy games, in which players compete to correctly predict realworld outcomes in sports, entertainment, and politics, have grown in popularity and now represent a significant po...
Greg Smith, Desney S. Tan, Bongshin Lee
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 11 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...